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Spin torque transfer random access memory (STT-RAM) is currently under development by most semiconductor manufacturers. By using the magnetization of a nanoscale patterned magnetic element to record information, STT-RAM combines multiple desirable features into a single memory technology: non-volatility, low-power, infinite write endurance, small size, scalability, and CMOS-backend fabrication capability. While standalone STT-RAM memory chips are already being shipped as a commercial product, the primary interest is driven by the need for a replacement for the conventional, large format, power­ hungry static RAM (SRAM) technology that is commonly employed for the cache memory on CPUs.

To write information in STT-RAM, the spin torque transfer effect is employed, whereby a large bias voltage applied to a tunnel junction with two magnetic electrodes can exert a torque on the electrode that stores the information, causing the magnetization to switch by 180 degrees. The polarity of the applied voltage determines the orientation of the magnetization in the memory electrode. Readout is accomplished via the tunneling magnetoresistance effect (TMR), whereby the effective resistance of the tunnel junction is small when the two magnetic electrodes are magnetized parallel to each other, whereas the resistance is much larger when the electrodes are magnetized antiparallel to each other.

Due to the detailed physics of the spin torque transfer process, the preferred orientation of the magnetization in the electrodes is perpendicular to the plane of the silicon wafer. This orientation significantly improves thermal stability while also reducing the voltage required to write a bit.

A significant challenge for the scaling of STT-RAM for integration into future product lines is the need to continuously reduce the inherent resistance of the magnetic tunnel junction (MTJ) as the bit area is reduced. Such a reduction is necessary because the decreased device cross-section increases the overall resistance of the memory, which diminishes the TMR signal needed to read the memory state. This requires further reductions in the tunnel junction thickness, which eventually results in significant reduction in write endurance, i.e. the number of write cycles the memory can withstand.

It has been proposed that a different physical process, the spin Hall effect (SHE), can be used to generate the torque necessary to write the STT-RAM bit, without the need to apply large bias voltages to the MTJ itself. With the SHE, current passing laterally through a nanowire consisting of heavy metals, such as Pt or Ta, generates a torque in a magnetic overlayer. The torque is oriented perpendicular to the direction of current flow, but in the plane of the semiconductor wafer. While such a torque is effective at switching in-plane orientated magnetic bits, it cannot switch the perpendicular oriented bits favored for STT-RAM applications.

Our invention overcomes this fundamental hurdle to the use of SHE for STT-RAM technology. We have found that replacement of the heavy metal nanowire with a transition-metal ferromagnetic (FM) nanowire separated from the memory element by a Cu spacer can efficiently generate a spin torque perpendicular to the semiconductor plane, thereby permitting SHE to switch perpendicular-oriented magnetic memory elements. The key physics at play in this new discovery is the large rotation of the torque via the spin-dependent reflection of spin-polarized electrons at the interface between a ferromagnet and Cu. The SHE produces a torque that is oriented transverse to the current flow direction but in the film plane. This torque is then rotated about the in-plane magnetization of the FM wire so that is it now oriented perpendicular to the film plane. The torque then enters the perpendicular memory element, causing it to switch via the spin torque transfer process. As such,this invention will greatly facilitate the use of SHE for STT­ RAM, and it will permit the semiconductor industry to maintain STT-RAM on the semiconductor road map for many generations to come.


Magnetic random access memories (MRAM) are currently under development as a new generation of computer memory. The Spin Hall effect (SHE) has been proposed to generate torque that can switch the magnetization and hence write information. Due to fundamental symmetry restrictions, the SHE by itself cannot generate the perpendicular torque necessary to efficiently switch perpendicularly oriented magnetic bits, which are currently used in MRAM technologies due to its high packing density and stability. This invention uses a magnetic thin film to efficiently rotate the torque due to the SHE, enabling the switching of perpendicular bits in a three terminal geometry.


The use of our invention would permit the future development of low-power, high-speed, high-density nonvolatile cache memory on advanced CMOS CPUs, including system on chip (SOC) architectures that are envisioned to be required for the future advancement of the Internet of Things (IoT). While the existing technology without the SHE is adequate for implementation at the less aggressive semiconductor nodes of 45 nm and above, an MTJ technology has not been found that can operate with 100% reliability at the 32 nm node or below. (The most advanced Intel processors are currently at the 14 nm node.) This is especially important since it is envisioned that future processors required for IoT applications will be fabricated primarily at the high-value 28 nm "golden node".

Justin Shaw, Hans Nembach, Xin, Fan, Eric Edwards, and Thomas Silva
Patent Number: 
Technology Type(s): 
Manufacturing, Electromagnetics, Electron Physics, Electronics, Physics, Nanotechnology
Internal Laboratory Ref #: 
Patent Issue Date: 
August 14, 2018
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