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Zero Order Overlay Targets

DConT2

Laboratory: National Institute of Standards and Technology (NIST)

Technology: Overlay targets that reduce defects in semiconductor manufacturing

Opportunity: Available for licensing exclusively or nonexclusively in any field of use

Details: Reduce defects in semiconductor fabrication by using overlay measurements and targets to tightly control layer-to-layer alignment. The new method uses slightly different overlay targets on each layer of a semiconductor structure. The targets consist of finely-spaced parallel lines, each having a slightly different spacing or pitch, thus enabling optical scans to determine overlay error.

Potential Applications: Used in semiconducting manufacturing to determine and correct overlay errors, resulting in structures that have approximately perfect overlay or alignment, thereby reducing the potential for defects that can cause short circuits and connection failures.

Benefits:

  • Flexible - Not limited to particular manufacturing processes or machines, means, methods or steps that perform essentially the same function or achieve the same results. No limitations on feature size and density.
  • Diverse applications - Allows optical overlay measurements to be performed using device-sized dimensions and very dense targets.
  • Easy to implement - Uses conventional imaging techniques.

Contact: Jack Pevenstein, Technology Partnership Office

For more details, view the original listing for this technology.

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