Available Technology

An Efficient, Highly Flexible Multi-Channel Digital Downconverter Architecture

The algorithm was developed to run in an FPGA at input data sampling rates of up to 1280 MHz. The current implementation takes a 1280 MHz real input and first breaks it up into seven 160 MHz complex channels each spaced 80 MHz apart. The eighth channel at baseband was not required for this implementation and lead to more optimization. Afterwords, four channels with independently tunable center frequencies and bandwidth settings are implemented. A future implementation in a larger Xilinx FPGA will hold up to 32 independent second stage channels.
Internal Laboratory Ref #: 
Patent Status: 
U.S. Government Purpose Release
Far West
Lab Representatives
Share to Facebook Share to Twitter Share to Google Plus Share to Linkedin