Available Technology

BSA 11-23: ASIC for Low Power ADC

This invention performs analog-to-digital conversion (ADC) combining (i) the concepts of BSA 06-01 (US Patent No. 7,187,316), which consists of using a sequence of identical current sources activated using a domino effect, (ii) the concept of feedback-controlled memory, and, if required, (iii) the concept of multiple conversion stages. The ADC also makes use of a novel precharging-sampling voltage-to-current converter. This ASIC for low pwer ADC allows achievement of high resolution with minimum requirements on clock, power, and area.
Patent Abstract: 
A method and apparatus for analog-to-digital converSIOn. An Analog-to-Digital Converter CADC) comprising M clockless ADCs is disclosed. Each ADC comprises a number of cell each of which comprises a first· switch, a second switch, a current sink and an inverter. An inverter of a cell changes state in response to a current associated with the input signal exceeding a threshold, thus switching on the next cell. Each ADC is enabled to perform analog-to-digital conversion on a residual current of a previous ADC after the previous ADC has completed its analog-to-digital conversion and disabled.
Benefits 
An analog-to-digital converter that is capable of meeting the requirements of lower power dissipation, smaller area, sampling rate capability of a few Msps, a 12-bit resolution, and lower requirement on clock. Low power consumption is required on systems which involve a large number of channels, and the upper limit for these systems may be a few milliwatt. In addition, for battery‐operated systems a low power ADC is required for longer battery life. ADC resolution is another important parameter which defines the minimum change in the analog input that can be discriminated by the ADC. For a moderate‐high resolution, 10 to 12 bit ADCs are typically required. Finally, the requirement on the clock (lowest possible clock frequency) and the available chip area are other factors contributing to the selection of the ADC topology. The power dissipated by the circuit equals the unit current times the number of discrete levels m in addition to the power dissipated by the voltage to current
applications 
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