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Clearer Imaging for Integrated Circuits

Method of Surface Preparation and Imaging for Integrated Circuits
US PATENT # 7,183,123 Method of surface preparation and imaging for integrated circuits 
US PATENT # 7,019,530 Method of surface preparation and imaging for integrated circuits

These semiconductor analysis techniques allow clear imaging of the components in an integrated circuit (IC) to be obtained from the top and backside perspectives without adding, altering, or removing elements to the IC.

These techniques enable clear imaging without staining or removing the upper layers of metal on the chip. This allows enhanced viewing of the interconnects, which reside at the lowest level of the chip, and analysis by multiple conventional imaging techniques.

IC analysis imaging techniques are used during failure analysis. Interconnects are a frequent source of failure in an integrated circuit; clear inspection greatly reduces the number of defective parts.



Click to view PDFs of these patents on the US Patent and Trademark Office website: Patent 7,183,123; Patent 7,019,530

  • Reverse engineering integrated circuits
  • Chemical laboratory analysis
  • Failure analysis, quality control
  • Counterfeit IC detection
Patent Number: 
7,183,123; 7,019,530
Patent Issue Date: 
February 27, 2007
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