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Electronics for a shock hardened data recorder

Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high mean time between failures (MTBF) figures in more benign environments.

Michael D. Haddon, Gabriel H. Soto

Patent Number: 
Patent Issue Date: 
June 6, 2003
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