Available Technology

Improved Enhancement of P-type/N-type Metal-Oxide-Semiconductor Field Effect Transistors Preserved over a Large Processing Temperature Range

There is need for higher currents in MOSFETs.
Patent Abstract: 
This invention consists of a tri-channel hetero-structure which has a tensile strained semiconductor layer, a compressively strained layer and a confining layer. The thicknesses and doping concentrations of the first two layers are optimized for wide ranges of performance enhancement. The third layer has a band offset with the second layer to confine carriers, and provides a diffusion barrier to the second layer over a large temperature range. A gate dielectric could be disposed over the first, the second or the third layer to form a MOSFET. A method of forming the above structure is also provided.
High hole and electron mobilities - High performance over a large processing temperature range
Eugene Fitzgerald
Lab Representatives
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