Available Technology

MASSIVELY PARALLEL WAFER LEVEL RELIABILITY SYSTEM

The massively parallel reliability (MPR) system is a compact measurement setup to perform highly accurate reliability tests on semiconductor devices. The innovations associated with the MPR system center on the densification and miniaturization of the semiconductor electrical characterization concept in three different ways. First, the miniaturization of the concept of a probe station into a small volume station allows for the use of multiple stations in a finite space. This multiplication of probe stations allows for the independence of test conditions, reduces the tests' overall duration, and decreases the cost of testing. The second innovation is the use of an innovative probe card that can withstand high test temperatures and contains a large number of test terminals. Third, the instrumentation electronics design provides the environmental conditions for the reliability tests (up  to 400 degrees C) and performs the measurements at high density and accuracy. The arrangement of these solutions makes the MPR system a groundbreaking tool in the area of semiconductor device reliability.

Inventors: 
Kin Cheung
Patent Number: 
10241149
Internal Laboratory Ref #: 
15-025
Patent Issue Date: 
March 26, 2019
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